000			03468cas a2200493 i 4500
001			11465620
003			CSPC
005			20260209090917.0
008			112624c2017 nyuqr p 0 a0eng c
010			_a 96640883 _zsn 95002109
022	0		_a1084-4309 _21
040			_aCSPC _beng _cCSPC _eeng
050	0	0	_aTK7869 _b.A25
210	0		_aACM transact. des. automat. electron. syst.
222		0	_aACM transactions on design automation of electronic systems
245	0	0	_aACM transactions on design automation of electronic systems.
264		1	_aNew York, NY : _bAssociation for Computing Machinery, _c2017.
300			_avolumes : _billustrations ; _c25 cm.
310			_aQuarterly
336			_atext _btxt _2rdacontent
337			_aunmediated _bn _2rdamedia
338			_avolume _bnc _2rdacarrier
362			_aVolume 22, Number 1
362			_aVolume 22, Number 2
362			_aVolume 22, Number 3
362			_aVolume 22, Number 4
504			_aIncludes bibliographical references
505	1		_aHierarchical dynamic thermal management method for high-performance many-core microprocessors -- Error-correcting sample preparation with cyber physical digital microfluidic lab-on-chip -- State assignment and optimization of ultra-high-speed FSMs utilizing tristate buffers -- A framework for block placement, migration, and fast searching in tiled-DNUCA architecture -- Obstacle-avoiding wind turbine placement for power loss and wake effect optimization -- Hardware trojans: lessons learned after one decade of research.
505	1		_aHoPE: hot-cacheline prediction for dynamic early decompression in compressed LLCs -- PeaPaw: performance and energy-aware partitioning of workload on heterogenous platforms -- CDTA: a comprehensive solution for counterfeit detection, traceability, and authentication in the lot supply chain -- Generation of transparent-scan sequences for diagnosis of scan chain faults -- Application-specific residential microgrid design methodology -- Layers assignment of escape buses with consecutive constraints in PCB Designs.
505	1		_aExploring energy- efficient cache design in emerging mobile platforms -- Scalable bandwidth shaping scheme via adaptively managed parallel heaps in manycore-based network processors -- Optimal scheduling ad allocation for IC design management and cost reduction -- Proof-carrying hardware via inductive invariants -- Automated integration of dual-edge clocking for low-power operation in nanometer nodes -- Design methodology of fault-tolerant custom 3D network-on-chip.
521			_aBachelor of Science in Electronics Engineering BSEE (CEA)
530			_aAlso issued in an annual CD-ROM.
650		0	_aElectronic systems _xDesign _xData processing _vPeriodicals.
650		0	_aElectronic circuit design _xData processing _vPeriodicals.
650		0	_aComputer-aided design _vPeriodicals.
650		0	_aIntegrated circuits _xDesign _xData processing _vPeriodicals.
650		7	_aComputer-aided design. _2fast _0(OCoLC)fst00872701
650		7	_aElectronic circuit design _xData processing. _2fast _0(OCoLC)fst00906866
650		7	_aIntegrated circuits _xDesign _xData processing. _2fast _0(OCoLC)fst00975544
655		0	_aComputer network resources.
700		1	_aChang, Naehyuck., _eeditor.
942			_2ddc _cSERIALS _n0 _e12 _h004 _iAc64 _kSER _m2017
999			_c28530 _d28530